This invention relates to phase lock loops employed in recording or recovering data.
Phase lock loops (PLL) are employed in data reading and recording. In the write mode, the PLL is employed to lock the recording circuitry onto the write clock signal. In the read mode, the PLL is employed to generate a clock signal, based on the recovered data pulses, for the recovery of data. Although data recovery and writing is accomplished at nominally the same frequency, there is often a substantial phase shift between the phase of recovered data and the phase of the write clock signal.
In typical data recovery systems, a preamble containing clocking information is written before the data. The PLL is designed to lock onto the recorded clocking information in the preamble to correct phase differences before the arrival of data. To avoid wasting valuable storage space due to large preambles, it is important that the PLL be designed to lock very rapidly onto the input signal. However, if the PLL operates too rapidly, it is likely to be sensitive to noise and pulse jitter, caused by imperfect heads and disks. Consequently, it is important that the PLL be designed to operate to lock onto phase changes as slowly as practical to ignore noise and pulse jitter. In most prior systems, the time constant of the PLL was designed at an optimum tradeoff to achieve a minimum of wasted space at a response time great enough to filter most signal noise. The present invention, however, is directed at apparatus to reduce the time required for phase lock, without affecting the time constant of the PLL. Particularly, the present invention is directed at reducing the initial phase error between the read and write modes.
Other techniques have been suggested for reducing the time for initial phase lock. U.S. Pat. No. 4,712,076 to R. D. Crouch et al, for example, describes a PLL which ordinarily locks onto every other data pulse, and which provides rapid lock-on by responding to every data pulse. However, the Crouch et al approach did not fully address the problem of rapid lock-on at mode shift, and the apparatus was slow in responding to changes in the normal data stream. IBM Technical Disclosure Bulletin, Vol 29, No. 2, pp. 553-555 describes a phase locked oscillator charge pump wherein the bandwidth/gain of the phase lock oscillator and charge pump current is increased during lock-in mode. The IBM approach, however, requires substantially more and complex circuitry, and may have difficulties due to switching transients. Other systems employ start-stop techniques wherein the voltage controlled oscillator (VCO) of the PLL is stopped and restarted at each lock-in mode shift. These systems suffer from transient difficulties, as well as problems in set-up time at restart. Examples of these stop-start systems may be found in the High-Performance Monolithic Data Separator, AIC-6225, from Adaptec, Inc. of Milpitas, California, and SSI 32D531 Data Separator and Write Precompensation Circuit from Silicon Inc. of Tustin, Calif. U.S. Pat. No. 4,005,479 to R. Hunnicutt et al. describes a system wherein the VCO is operated at a finite multiple (N) of the clock signal and the multiplied signal is frequency divided by the same number. The divider is reset at each mode shift so the maximum phase error will be .pi./N radians. However, operating the VCO at a multiple of the clock signal can lead to problems, especially where the intended data recovery is of the order to 100 MHz.
It is, therefore, an object of the present invention to provide a phase lock loop apparatus capable of locking onto an input signal in a minimum period of time, without reducing the response time of the phase lock loop so as to make it more sensitive to noise and pulse jitter.
Another object of the present invention is to provide apparatus for a phase lock loop to reduce initial phase error upon mode switching between input signals.